Qorvo – Principal Analog IC Design Engineer – San Jose, CA

September 18, 2022

Job Description

Job title: Principal Analog IC Design Engineer

Company: Qorvo

Job description: Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers’ most complex technical challenges. Qorvo serves diverse high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our diverse and innovative team is helping connect, protect and power our planet.

High Performance Analog (HPA) is a leading supplier of RF and power management solutions for infrastructure, defense & aerospace, automotive power and other high-growth markets. HPA’s diverse portfolio of differentiated technologies and products supports multi-year market drivers such as electrification, renewable energy, the increasing semiconductor spend in defense and 5G deployments outside of China.

Principal Analog IC Design Engineer


Qorvo is looking for a highly motivated, and experienced Analog IC Engineer responsible for the design and development of innovative, leading-edge integrated circuits used in Qorvo’s Power Management products. You will be a key member of an integrated product development team that includes marketing, program management, product engineering, package engineering, test engineering, applications engineering, manufacturing, operations, quality and reliability, and senior management.


  • Collaborates with internal system engineers to architect/define/specify new product definitions for world-class analog power management ICs
  • Select the optimal topology and composition of designs to achieve the best possible performance, yield and testability
  • Responsible for design and simulation per defined product functionalities and specifications
  • Participate in design reviews, including presenting expected and/or actual results
  • Work with test and characterization engineers to develop a thorough characterization and production test strategy as well as troubleshoot analog/digital design issues
  • Deliver design release notes and documentation for product characterization
  • Lead, coordinate and mentor with designers in Asia


  • MSEE or PhD in Electrical Engineering, 15+ years of experience in analog and mixed mode circuit design and development
  • At least eight years of relevant experience
  • Candidates with HV GaN and SiC gate driver design experience preferred
  • Experience in Power Management design techniques including layout and parasitic extraction expertise is desirable
  • Extensive experience designing with Cadence, MATLAB LabVIEW optional ADS or similar tools
  • Good communication skills, be able to work remote and independently
  • Candidates with successful production release of Power Management ICs would be highly considered
  • Strong leadership ability; must work well in teams and outside the job function; must be able to mentor less experienced engineers


We are Qorvo. We do more than create innovative RF solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what’s next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.


Qorvo is an E-Verify Employer. For more information, please see the and posters.

Expected salary:

Location: San Jose, CA

Job date: Sun, 18 Sep 2022 04:30:52 GMT


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